Linked Data Explorerhttp://worldcat.org/entity/work/id/34103906
Information technology microprocessor systems : control and status registers (CSR) Architecture for microcomputer buses
"The document structure and notation are described, and the objectives and scope of the CSR Architecture are outlined. Transition set requirements, node addressing, node architectures, unit architectures, and CSR definitions are set forth. The ROM specification and bus standard requirements are covered"--Page 2 of cover.
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- http://id.loc.gov/authorities/names/n79053217
- http://viaf.org/viaf/144231286
- http://viaf.org/viaf/123926298
- http://viaf.org/viaf/133254239
- http://viaf.org/viaf/149705257
- http://id.loc.gov/authorities/names/n81008302
- http://id.loc.gov/authorities/names/n79034445
- http://experiment.worldcat.org/entity/work/data/34103906#Organization/ieee_computer_society_microprocessor_and_microcomputer_standards_committee
- http://id.loc.gov/authorities/names/n79031437
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- ""The document structure and notation are described, and the objectives and scope of the CSR Architecture are outlined. Transition set requirements, node addressing, node architectures, unit architectures, and CSR definitions are set forth. The ROM specification and bus standard requirements are covered"--Page 2 of cover."@en
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- "Information technology microprocessor systems : control and status registers (CSR) Architecture for microcomputer buses"@en
- "Information technology - Microprocessor systems - Control and status registers (CSR) architecture for microcomputer buses"
- "Information technology -- microprocessor systems -- control and status registers (CSR) Architecture for microcomputer buses"@en